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71M6521DE/DH/FE Data Sheet
On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate
vector address, if the following conditions are met:
?
?
?
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1 .
Special Function Registers for Interrupts:
Interrupt Enable 0 register ( IE0 )
MSB
LSB
EAL
WDT
ES0
ET1
EX1
ET0
EX0
Table 35: The IEN0 Register
Bit
IEN0.7
IEN0.6
IEN0.5
IEN0.4
IEN0.3
IEN0.2
IEN0.1
IEN0.0
Symbol
EAL
WDT
-
ES0
ET1
EX1
ET0
EX0
Function
EAL =0 – disable all interrupts
Not used for interrupt control
ES0 =0 – disable serial channel 0 interrupt
ET1 =0 – disable timer 1 overflow interrupt
EX1 =0 – disable external interrupt 1
ET0 =0 – disable timer 0 overflow interrupt
EX0 =0 – disable external interrupt 0
Table 36: The IEN0 Bit Functions
Interrupt Enable 1 Register ( IEN1 )
MSB
LSB
SWDT
EX6
EX5
EX4
EX3
EX2
Table 37: The IEN1 Register
Bit
IEN1.7
IEN1.6
IEN1.5
IEN1.4
IEN1.3
IEN1.2
IEN1.1
IEN1.0
Symbol
-
SWDT
EX6
EX5
EX4
EX3
EX2
-
Function
Not used for interrupt control
EX6 =0 – disable external interrupt 6
EX5 =0 – disable external interrupt 5
EX4 =0 – disable external interrupt 4
EX3 =0 – disable external interrupt 3
EX2 =0 – disable external interrupt 2
Table 38: The IEN1 Bit Functions
Rev 3
Page: 31 of 107
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